In today's high-speed communication channels, many chip-to-chip interfaces utilize CML drivers. The CML drivers of one chip drive outgoing communication signals to another chip. CML drivers typically use an NMOS differential pair that steers a differential current to a single or double terminated differential resistance, such as a 50 ohm termination resistance connected to the power supply. In order to interface between chips which may utilize different power supply voltages and/or different process technologies, it is desirable to AC couple the CML drivers of the sending chip to the input of the receiving chip. AC coupling may also permit the designer to take advantage of high-speed process technology (low-voltage devices) that may not otherwise interface with the CML drivers.
However, the use of AC coupling presents various design challenges. For example, the addition of off-chip bypass capacitors leads to undesirable parasitics. On the other hand, the relatively large amount of capacitance required makes it difficult to integrate the capacitors on the chip.
Another difficulty associated with the use of CML drivers is the common-mode noise generated by CML drivers.
It is desirable in view of the foregoing to provide for chip-to-chip interfacing using CML drivers and AC coupling between chips, while avoiding the aforementioned capacitor design and common-mode noise difficulties.